The present invention relates to a timing circuit of an optical receiver in a high-speed optical communication system and, more particularly, to a timing circuit for generating a clock signal which indicates a timing for discriminating a received data signal.
The optical receiver in a high-speed optical communication system converts a data waveform which is distorted during transmission or a data waveform carrying noise into a clean waveform, in other words, executes what is called data regeneration. In such data regeneration, the optical receiver generates a clock signal by using a received data signal, and a discriminating portion reproduces data on the basis of the timing with which the clock signal is generated.
FIG. 19 shows an example of an optical receiver in an optical communication system. The reference numeral 1 represents an optoelectric conversion circuit for converting an optical signal into an electric signal, 2 an equalizing amplifier for equalizing and amplifying a data signal of, for example, 10 Gbps which is output from the optoelectric conversion circuit 1, 3 a timing circuit for extracting a clock signal, which has a frequency same as that of the bit rate, from the data signal received, and 4 a discriminating circuit for discriminating the data signal by using the clock signal which is output from the timing circuit 3. The optical signal transmitted through an optical fiber is converted by the optoelectric conversion circuit 1 into an electric signal, and equalized and amplified by the equalizing amplifier 2. The timing circuit 3 extracts a clock signal from the equalized waveform and triggers the discriminating circuit 4. The discriminating circuit 4 judges whether the equalized waveform is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d at the point of time of sampling, and restores the original code pulse. Since there is a change in the delay time in the transmission line or the like, the discriminating circuit 4 is triggered by a clock signal which is synchronous with the data signal received.
In optical communication, an NRZ code, an RZ code, etc. is used as a transmission line code. In an optical communication apparatus of not less than 600 Mbps, an NRZ code in which the bands required for the electric circuit and the optical device are not strict is generally used. When an NRZ code is used, since a data signal contains no clock component, it is necessary to generate a clock signal by processing the data signal. A conventional timing circuit of an optical receiver for generating such a clock signal has either (1) a structure (FIG. 20) using a timing filter or (2) a structure (FIG. 21) using a PLL.
FIG. 20 shows the structure of a timing circuit using a timing filter. The timing circuit is composed of a nonlinear extractor 110 for detecting the rising edge and the falling edge of an input data signal, a bandpass filter 111 having a center frequency identical with the bit rate of the data signal, and a limiting amplifier 112 as a narrow band amplifier. The nonlinear extractor 110 includes a branching circuit 110a for branching a data signal in two directions, a delay circuit 110b for delaying a first branched data signal by a predetermined time (xc2xd of the time equivalent to 1 bit), and an EXOR (Exclusive OR) circuit 110c for executing an exclusive OR operation of the second branched data signal and the output signal of the delay circuit 110b and generating an edge signal having a pulse at the rising edge and the falling edge of the data signal. FIG. 22 shows an operating waveform. The EXOR circuit 110c detects the rising edge and the falling edge of the data signal and generates a pulse, the bandpass filter 111 extracts the clock component having the same frequency as that of the bit rate of the data signal, and the limiting amplifier 112 amplifies the clock component to a predetermined amplitude. Herein, the structure of the nonlinear extractor 110 having a combination of a differentiating circuit and a full-wave rectifier has also been proposed.
FIG. 21 shows the structure of a timing circuit using a PLL. The timing circuit is provided with a phase detector 121 for comparing the phases of a data signal and a clock signal and outputting the phase difference, a level converter 122 for converting the output level of the phase detector 121, a loop filter 123 for smoothing the voltage signal corresponding to the phase difference which is output from the level converter 122, and a voltage controlled oscillator (VCO) 124 for generating a clock signal having the frequency corresponding to the output of the loop filter 123. As examples of the structure of the phase detector 121, those shown in FIGS. 23 and 24 have been proposed.
The phase detector 121 shown in FIG. 23 compares the phase of a data signal DATA with the phase of a clock signal both at the rising edge and the falling edge of the data signal DATA, synthesizes the phase differences of the data signal at the rising edge and the falling edge, and executes PLL control. The phase detector 121 is provided with two D flip flops (D-FFs) 201, 202 which function as phase detectors, an inverting gate 203 for inverting the logic of the data signal DATA and an adder 204 for adding the outputs of the D-FFs 201, 202.
The D-FF stores the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the clock signal CLOCK input to a data input terminal (terminal D) at the rising edge of each data signal DATA, *DATA input to a clock input terminal (terminal C), and holds the level until the next data signal rises. Therefore, when the phase of the clock signal CLOCK lags behind that of the data signal DATA, as shown in (1) of FIG. 25, the D-FF outputs a low-level (EL) signal D-FF out. On the other hand, when the phase of the clock signal CLOCK leads that of the data signal DATA, as shown in (2) of FIG. 25, the D-FF outputs a high-level (EH) signal D-FF out.
In this manner, the D-FF 201 outputs a signal corresponding to the phase of the clock signal at the rising edge of the data signal, while the D-FF 202 outputs a signal corresponding to the phase of the clock signal at the falling edge of the data signal. The adder 204 synthesizes these signals and outputs a phase detection signal PDS. The timing circuit having a PLL structure controls the phase of the clock signal so that the phase detection signal PDS has a preset level. For example, when the duty of the data signal varies to less than 100%, the rising edge of the data signal lags behind that of the clock signal and the falling edge of the data signal leads that of the clock signal. The phase detector 121 outputs the phase detection signal PDS which corresponds to the difference between the amount of lag and the amount of lead and the timing circuit outputs the clock signal CLOCK so that the amount of lag may be equal to the amount of lead.
The phase detector shown in FIG. 24 detects the rising edge and the falling edge of a data signal DATA and compares the phases of a rising edge signal EGU and a falling edge signal EGD with the phase of a clock signal CLOCK. The phase detector is provided with an edge detector 251 and a D-FF 252. The D-FF 252 outputs the level of the clock signal CLOCK as a phase detection signal PDS when the rising edge signal EGU and the falling edge signal EGD are produced. Since the phase detector is provided with the edge detector 251, the same operation as that of the phase detector shown in FIG. 23 is carried out with only one D-FF.
FIG. 26 is an explanatory view of the relationship between the phase difference xcex8 between the clock signal CLOCK and the data signal DATA and the output (phase detection signal PDS) of the phase detector. In this drawing, the duty of the data signal DATA is 100%, and the phase of the data signal DATA leads the phase of the clock signal CLOCK. The word xe2x80x9cdutyxe2x80x9d will be defined strictly later, but briefly speaking, when the bit rate is f(=1/T), the duty is the ratio of the period T1 of a data signal xe2x80x9c1xe2x80x9d and T. When the duty is 100% (T=T1), as shown in FIG. 26, the phase relationship between the rising edge of the data signal and the clock signal is the same with the phase relationship between the falling edge of the data signal and the clock signal. Consequently, the waveform of the output (phase detection signal PDS) of the phase detector is a rectangular waveform which alternates with a phase difference period of T/2.
It is possible to fix the phase relationship between the clock signal CLOCK and the data signal DATA by controlling the phase of the clock signal so that the clock signal rises at the position at which the data signal DATA is switched over from a LOW level to a HIGH level. However, in the phase detection signal PDS, the switching characteristic between the LOW level and the HIGH level is steep (the level is binary), continuous phase control of the clock signal is impossible, so that the control becomes unstable. That is, if the clock signal is produced by using the binary phase detection signal PDS and the phases of the data signal and the clock signal are made coincident with each other by feeding the clock signal back to the phase detector, the control becomes unstable at a discontinuous point of the phase detection signal PDS. As a countermeasure, a microsignal having a low frequency is superimposed on the clock input terminal (terminal C) of the D-FF for the purpose of modulation. In this manner, it is possible to provide the phase of the data signal input to the clock input terminal C with perturbation, which enables the phase detection signal PDS to gently incline with the phase difference xcex8 as indicated with the broken line in FIG. 26. Stable control is thus enabled.
In a conventional high-speed communication system, an NRZ code is used, and the duty is approximately 100% before and after transmission. However, with an increase in the transmission speed, the pulse width per bit becomes narrow and the transmission is influenced by a nonlinear effect and the wavelength dispersion of the optical fiber, which leads to a large distortion of the transmission waveform. FIG. 27A shows the waveform of light signal on the transmitter side when the duty is 100% (T=T1), FIG. 27B shows the waveform of transmission light (on the left side) and the equalized waveform (on the right side) when the duty is less than 100% by the distortion, and FIG. 27C shows the waveform of transmission light (on the left side) and the equalized waveform when the duty is more than 100% by the distortion.
As is clear from these drawings, the duty of the received waveform greatly changes due to waveform distortion, and the change is 50% to 120% depending upon the transmission conditions. The duty, by reference to FIG. 27A, is defined as the ratio of the duration (T1) of one pulse at the center of the crest value and one time slot interval (T).
Although it is possible to relieve the distortion of the transmission waveform by inserting a dispersion compensating fiber or the like into a transmission line, since a high cost is required, it is desirable to enable the longest-possible-distance transmission without using such an accessory part. Thus, an optical receiver is required to receive a largely distorted waveform without the need for compensating the wavelength dispersion and accurately reproduce the original data.
As shown in the literature (xe2x80x9cComparison between codes in IM-DD Optical Amplifier Repeater Systemxe2x80x9d by Saito et al, pp 4 to 77, The Institute of Electronics, Information and Communication Engineers, Spring 1992), the transmission characteristics are improved by using an RZ code under some transmission conditions. A timing circuit which can use both an RZ code and an NRZ code is therefore desirable. When an RZ code is used, the duty of the waveform input to an optical receiver is 50%.
A change in the duty exerts a deleterious influence on the operation of a timing circuit. In the timing circuit using a timing filter shown in FIG. 20, if the duty reduces, the phase of the data rising edge detection pulse RP which reaches to a HIGH level at the rising edge of the data signal lags while the phase of the data falling edge detection pulse TP which reaches to a HIGH level at the falling edge of the data signal leads, as shown in FIG. 22. These pulses are synthesized, and a clock component is extracted from the synthesized pulse. Although the phase of the extracted clock component does not change, since there is a cancelled component, the clock component extracted is reduced. When the duty becomes 50%, the phases of the rising edge detection pulse and the falling edge detection pulse become opposite, so that the clock component of the bit rate becomes zero and the nonlinear extractor 110 does not operate normally.
Each of FIGS. 28A, 28B and 28C shows the waveform of the signal output from the EXOR circuit 110c in a case where duty is 100%, 75% and 50% respectively. By reference to FIG. 28C, it is apparent that a clock component whose frequency is identical with that of the bit rate of the data disappears from the EXOR output signal. Like the decrease of the duty, the clock component reduces in accordance with the increase of the duty. FIG. 29 shows the relationship between the duty of the data signal and an extracted clock component.
In the timing circuit using a PLL shown in FIG. 21, if the phase detector 121 has the structure shown in FIG. 24, the timing circuit does not operate normally when the duty becomes 50% in the same way as the timing circuit using a timing filter. If the phase detector 121 has the structure shown in FIG. 23, when the duty becomes small (or large), the waveform of the phase detection signal PDS is such as that shown in (6) of FIG. 30, and an intermediate level MLV between the HIGH level and the LOW level generates. The intermediate level MLV has a length represented by:
(100-duty(%))xc3x97360xc2x0/100.
In FIG. 30,
(1) shows the clock signal CLOCK input to the terminals D of the D-FFs 201, 202;
(2) shows the data signal DATA input to the terminal C of the D-FF 201, wherein the broken line shows the data signal DATA when the duty is 100%, and the solid line the data signal DATA when the duty is less than 100%;
(3) shows the characteristic which shows the relationship between the output (rising edge detection output) of the D-FF 201 and the phase difference xcex8;
(4) shows the inverting data signal *DATA (the inverting signal of the data signal) input to the terminal C of the D-FF 202;
(5) shows the characteristic which shows the relationship between the output (falling edge detection output) of the D-FF 202 and the phase difference xcex8; and
(6) shows the phase detection output (phase detection signal PDS) obtained by synthesizing the output of the D-FFs 201, 202.
In the waveforms shown in FIG. 30, no low-frequency signal is superimposed on the clock input terminal C of the D-FF, so that the phase of the data signal is not provided with perturbation. Actually, however, a low-frequency signal is applied to the clock input terminal C of the D-FF, so that each D-FF output has a gentle inclination (see FIG. 26). In order to make the relationship between the data signal DATA and the clock signal CLOCK constant irrespective of the duty, it is desirable to fix the phase at the point A in (6) of FIG. 30. In order to detect the point A, it is necessary to increase the amount of perturbation which is applied to the phase of the data signal input to the clock input terminal C by the amount corresponding to the difference between the current duty and the duty of 100%. In other words, in order to search for the desired fixed point, the low-frequency component superimposed to the clock reference terminal C is increased. However, there are limits to the amount of phase shift realized by varying the voltage applied to the clock reference terminal C, and it is difficult to secure a large amount of phase shift.
Accordingly, it is an object of the present invention to eliminate the above-described problems in the related art and to provide a timing circuit which is capable of stably operating even if the input waveform of a data signal has a large distortion and the duty of the data signal greatly changes.
It is another object of the present invention to provide a timing circuit which is capable of maintaining the duty of a data signal at 100% even if the data signal has a distortion.
It is still another object of the present invention to provide a timing circuit having a simple structure which is capable of accurately operating even if the duty of a data signal changes.
To achieve these ends, in a first aspect of the present invention, there is provided a timing circuit for generating a clock signal which indicates a timing for discriminating a data signal. The timing circuit comprises a branching means for branching a data signal in two directions, a duty monitoring means for monitoring the duty of a first data signal output from the branching means, and a duty varying means for varying the duty of a second data signal output from the branching means. The timing circuit further comprises a control circuit for controlling the duty varying means on the basis of the duty information output from the duty monitoring means so that the duty of the data signal to be output has a predetermined value, and a clock signal generating means for generating a clock signal which is synchronous with the data signal output from the duty varying means and indicating a timing for discriminating the data signal.
In a second aspect of the present invention, there is provided a timing circuit for generating a clock signal which indicates a timing for discriminating a data signal, wherein the timing circuit comprises a duty varying means for varying the duty of a data signal, a duty monitoring means for monitoring the duty of a data signal output from the duty varying means, and a control circuit for controlling the duty varying means so that the duty of the data signal output from the duty monitoring means has a predetermined value. The timing circuit further comprises a clock signal generating means for generating a clock signal which is synchronous with the data signal output from the duty monitoring means and indicates a timing for discriminating the data signal.
In a third aspect of the present invention, wherein there is provided a timing circuit for generating a clock signal which indicates a timing for discriminating a data signal, the timing circuit comprises a duty varying means for varying the duty of a data signal, a clock component detector for detecting the magnitude of a clock component extracted from the data signal which is output from the duty varying means, and a control circuit for controlling the duty varying means so that the extracted clock component is at its maximum. The timing circuit further comprises a clock signal generating means for generating a clock signal which is synchronous with the data signal output from the duty varying means and indicates a timing for discriminating the data signal.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.